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回复 1# yovish

This is normal for the logic gate circuit, otherwise  you should use a flip-flop or latch with clk  .

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回复 3# yovish

I don’t understand.
In theory, any input signal A/B cannot be changed at the same time(Absolute synchronization). For logic gate circuits, Y may have a uncertain pulse signal before A andB inputs is stable .

the reading method of the programmer:  Delay to the A/B signal is stable, then read the value of Y