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When I was creating vectors for logic tests of various ICs, I noticed some problems when switching signals.
I will illustrate it on the example of the test of one logic gate of the TTL 7408 integrated circuit (quad 2-input AND gates).
In this analysis, the idea is to show what signals appear at the logic gate output when sending the "0" and "1" signals alternately to the gate inputs. When the "0" signal is sent to the "A" input, and the "1" signal to the "B" input, and then vice versa, the "1" signal is sent to the "A" input, and the "0" signal to the "B" input, then at the "Y" output there should be a "L" (logical zero) signal all the time. But it is not because there is a short burst (impulse) as shown in detail X1. Sometimes there is an impulse with additional noise, this is shown in detail X2.
Often, such an impulse does not bother with tests, where there are usually only logic gates, but the problem is significant when such gates control flip-flops.
If this problem cannot be fixed then some logic tests should be changed, despite being logically compatible with the IC datasheets.
It is best to check the tests with real integrated circuits, but this will not always be possible.
The tests were performed with an 8-input logic analyzer with a sampling frequency of 24MHz. |
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