Unfortunately, but logic testing in TL-866II+/T56 programmers, at present, does not facilitate memory testing for several reasons:
1. the maximum number of test lines in the logic vector is 512;
2. lack of instructions for sequential address insertion, each address must be entered bit by bit manually;
3. no additional editing functions in the vector, e.g. deleting single or selected lines, pasting lines, etc, etc.
At the moment, it is easier to make a memory tester yourself using e.g. Arduino, ESP or STM.
I also hope that the company will soon change its mind and quickly add various facilities. |
