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标题: Problematic impulses [打印本页]

作者: yovish 时间: 2021-8-10 06:13 标题: Problematic impulses

When I was creating vectors for logic tests of various ICs, I noticed some problems when switching signals.
I will illustrate it on the example of the test of one logic gate of the TTL 7408 integrated circuit (quad 2-input AND gates).
In this analysis, the idea is to show what signals appear at the logic gate output when sending the "0" and "1" signals alternately to the gate inputs. When the "0" signal is sent to the "A" input, and the "1" signal to the "B" input, and then vice versa, the "1" signal is sent to the "A" input, and the "0" signal to the "B" input, then at the "Y" output there should be a "L" (logical zero) signal all the time. But it is not because there is a short burst (impulse) as shown in detail X1. Sometimes there is an impulse with additional noise, this is shown in detail X2.
Often, such an impulse does not bother with tests, where there are usually only logic gates, but the problem is significant when such gates control flip-flops.
If this problem cannot be fixed then some logic tests should be changed, despite being logically compatible with the IC datasheets.
It is best to check the tests with real integrated circuits, but this will not always be possible.

The tests were performed with an 8-input logic analyzer with a sampling frequency of 24MHz.

图片附件: 7408 One Gate.JPG (2021-8-10 06:09, 18.29 KB) / 下载次数 12296
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图片附件: 7408 Impuls Test - Signal analysis.jpg (2021-8-10 06:09, 47.4 KB) / 下载次数 12415
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图片附件: 7408 Impuls Test - Detail X1.jpg (2021-8-10 06:10, 43.44 KB) / 下载次数 12319
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图片附件: 7408 Impuls Test - Detail X2.jpg (2021-8-10 06:10, 45.33 KB) / 下载次数 12290
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图片附件: 7408 Impuls Test - Logic Vector.jpg (2021-8-10 06:10, 325.47 KB) / 下载次数 13004
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图片附件: 7408 Impuls Test - Logic Test.jpg (2021-8-10 06:11, 309.97 KB) / 下载次数 12897
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图片附件: 7408 Impuls Test - Equipment.jpg (2021-8-10 06:11, 373.24 KB) / 下载次数 12860
http://forums.xgecu.com/attachment.php?aid=870&k=c8aa78c8812275471b459f347f11baaa&t=1732299731&sid=YjWS6s

作者: admin 时间: 2021-8-10 13:17

回复 1# yovish

This is normal for the logic gate circuit, otherwise you should use a flip-flop or latch with clk .

作者: yovish 时间: 2021-8-11 04:53

回复 2# admin

Please note that I do not mean problems with logic analyzes of some logic circuits, I am showing what problems occur during logic tests performed with your programmer.

I realize that it may not be possible to fix it quickly, or it may not even be possible to fix it at any time.

I wonder why these pulses only occur in certain combinations of signals. Maybe the impulses are affected by the different ramp and fall characteristics of the signal on different pins?

Either way, we all need to carefully create logical vectors.

作者: admin 时间: 2021-8-11 07:28

回复 3# yovish

I don’t understand.
In theory, any input signal A/B cannot be changed at the same time(Absolute synchronization). For logic gate circuits, Y may have a uncertain pulse signal before A andB inputs is stable .

the reading method of the programmer: Delay to the A/B signal is stable, then read the value of Y

作者: yovish 时间: 2021-8-11 22:19

Yes, it is true that until the inputs stabilize, there may be an unpredictable signal at the outputs.
Therefore, you should carefully select signals for logic tests, and it is best to do tests with real integrated circuits. Although I do not exclude doing tests, only on the basis of data sheets.

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