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标题: New Logic Test - 7419 Vector Table [打印本页]

作者: yovish 时间: 2021-5-22 04:05 标题: New Logic Test - 7419 Vector Table

Enclosed is the new layout to be added to the logic tests.
The test was performed on the M74LS19P (hex Schmitt-Trigger inverters) chip from Mitsubishi.

图片附件: 7419 - Logic Vector.jpg (2021-5-22 04:04, 214.83 KB) / 下载次数 9441
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图片附件: 7419 - Logic Test.jpg (2021-5-22 04:05, 257.78 KB) / 下载次数 9561
http://forums.xgecu.com/attachment.php?aid=558&k=7b77a22e705519e2092cf10337bfb3cc&t=1714355232&sid=4xPwpX

图片附件: M74LS19P.jpg (2021-5-22 04:05, 315.72 KB) / 下载次数 9616
http://forums.xgecu.com/attachment.php?aid=559&k=b018c55208bcc7203275489095704fcf&t=1714355232&sid=4xPwpX

附件: SN74LS19A, SN74LS24A.pdf (2021-5-22 04:05, 1.12 MB) / 下载次数 7447
http://forums.xgecu.com/attachment.php?aid=560&k=a5084a930fe3e70f678aef484fce3114&t=1714355232&sid=4xPwpX

附件: 7419.lgc (2021-5-22 04:05, 2.11 KB) / 下载次数 35579
http://forums.xgecu.com/attachment.php?aid=561&k=254ef4dc7f6b2d378dbb57e9f08028c1&t=1714355232&sid=4xPwpX

作者: admin 时间: 2021-5-22 09:22

回复 1# yovish

Thank you for your hard work.
It is recommended to add more vector test lines to detect short circuits between two adjacent logic cells.
As shown below:

图片附件: 阿里旺旺图片20210522092912.jpg (2021-5-22 09:22, 33.18 KB) / 下载次数 9459
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作者: yovish 时间: 2021-5-22 19:04

It would be best to test all possible combinations of inputs and outputs on 6 gates (2^6=64), but I thought that's what you wanted, example of similar tests: 4009, 4069, 4584, 7404, 7405*, 7406*, 7414, 7416...
Creating tests with lots of lines is a pain in this release and you ignore various suggestions for improving the software ...
I am a supporter of full tests, but it seemed to me that it is about initial tests of the logic of the integrated circuit, and everyone can write exact and more precise tests by themselves.
Yes, otherwise I am attaching a full test of the 7419 (it can also be used for other integrated circuits of the same design)...

图片附件: 7419 (Full test) - Logic Vector.jpg (2021-5-22 19:03, 643.65 KB) / 下载次数 10040
http://forums.xgecu.com/attachment.php?aid=569&k=eb4058db8c2548243fc7057d76064cb5&t=1714355232&sid=4xPwpX

图片附件: 7419 (Full test) - Logic Test.jpg (2021-5-22 19:03, 302 KB) / 下载次数 9660
http://forums.xgecu.com/attachment.php?aid=570&k=5b80f3dbbb8c9871e263516f90fe4798&t=1714355232&sid=4xPwpX

附件: 7419 (Full test).lgc (2021-5-22 19:04, 3.56 KB) / 下载次数 36211
http://forums.xgecu.com/attachment.php?aid=571&k=946eb4b9520c63aa5c9ffc1dcf9ddbee&t=1714355232&sid=4xPwpX

作者: admin 时间: 2021-5-23 10:04

回复 3# yovish

Yes, it is a lot of work to perform all the combined tests. Generally, only the logic combination test of nearby pins is required..

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