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标题: New Logic Test - 74642 Vector Table [打印本页]

作者: yovish 时间: 2021-4-22 04:08 标题: New Logic Test - 74642 Vector Table

Enclosed is the new layout to be added to the logic tests.
The test was performed on the 74LS642-1N (invert. octal bus transceiver with 3-state comp. out, open collector) chip from Signetics.

图片附件: 74642 - Logic Vector.jpg (2021-4-22 04:07, 273.38 KB) / 下载次数 9420
http://forums.xgecu.com/attachment.php?aid=457&k=655a8dc9aa766dac6ef1dab6977e3747&t=1747640662&sid=s5Svyh

图片附件: 74642 - Logic Test.jpg (2021-4-22 04:07, 242.22 KB) / 下载次数 9226
http://forums.xgecu.com/attachment.php?aid=458&k=a9a1c3ad8b313c41c896baaf9fc60ebb&t=1747640662&sid=s5Svyh

图片附件: 74LS642-1N.jpg (2021-4-22 04:07, 196.02 KB) / 下载次数 9255
http://forums.xgecu.com/attachment.php?aid=459&k=e771adb73980de805b0c270bf13bc937&t=1747640662&sid=s5Svyh

附件: 74LS640, 641, 642 i 645.pdf (2021-4-22 04:07, 122.47 KB) / 下载次数 7778
http://forums.xgecu.com/attachment.php?aid=460&k=f4912bf59643c68252cb5417267f8017&t=1747640662&sid=s5Svyh

附件: 74642.lgc (2021-4-22 04:08, 2.18 KB) / 下载次数 34922
http://forums.xgecu.com/attachment.php?aid=461&k=a0355680378a5a551b2c92435618a760&t=1747640662&sid=s5Svyh

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