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标题: New type of clock signal [打印本页]

作者: yovish 时间: 2021-4-6 02:37 标题: New type of clock signal

Is it possible to introduce a second type of clock signal as shown in the picture?

Now there is only a signal type 010 ("C"), but adding a signal 101 ("K") would increase the possibilities of testing digital circuits.

图片附件: C&K_clocks.jpg (2021-4-6 02:37, 64.63 KB) / 下载次数 16990
http://forums.xgecu.com/attachment.php?aid=362&k=a6862fedfcd965187623a7f048e2ff80&t=1732594536&sid=BvuZv6

图片附件: TL866II Clock Test.jpg (2021-4-6 03:05, 85.98 KB) / 下载次数 17031
http://forums.xgecu.com/attachment.php?aid=363&k=46d65e40ebd107a496ba709989594a23&t=1732594536&sid=BvuZv6

作者: admin 时间: 2021-4-6 15:44

1. set CLK PIN to 1
2 set CLK PIN to 0

3 set CLK PIN to 1

作者: yovish 时间: 2021-4-6 17:03

I would suggest considering 2 new signals: "U" - Up (01) and "D" - Down (10) ...

作者: yovish 时间: 2021-4-6 17:25

回复 2# admin

It is about signals that change during other signals...
This is easier to understand when you work with digital signals...

图片附件: New signals.jpg (2021-4-6 17:48, 20.99 KB) / 下载次数 16583
http://forums.xgecu.com/attachment.php?aid=365&k=6476d4208cca8b4c002f94ce9af9b59e&t=1732594536&sid=BvuZv6

作者: yovish 时间: 2021-6-19 07:34

Competitive companies know that it is worth being more flexible and you need to improve your products...

Here is a description of the signals for logic tests.

; Characters for testing vector are as follows:
;                            G...apply GND
;                            V...apply VCC
;                            X...Don't care
;                            0...input low level
;                            1...input high level
;                            C...input L-H-L puls
;                            K...input H-L-H puls
;                            L...expected output is low level
;                            H...expected output is high level
;                            Z...expected output is float

作者: admin 时间: 2021-6-20 09:09

回复 5# yovish

Later, when we have time, we will add this function .
Temporary method： 3-items vector table 1 - 0 - 1

作者: yovish 时间: 2021-6-21 03:41

回复 6# admin

Just don't underestimate it and don't forget it. Please consider also other quite simple improvements in logic tests (eg clock signal "U" - up "01" and "D" - down "10" and other easy modifications to improve the editing of logical tests).
Your programmers, at least in logic tests, can become much better than the much more expensive competition, costing $ 500-1000.
I still have at least 30-40 new tests to do, which will further enrich the list of logic integrated circuits tested.

作者: admin 时间: 2021-6-21 08:47

回复 7# yovish

You are right, we will improve it in the future

作者: yovish 时间: 2021-8-11 05:57

Thank you very much!

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