返回列表 发帖

JEDEC vectors

The TL866II + device contains the necessary tools to program the GAL/PAL chips. I know that after programming the GAL/PAL, the chip must be checked for compliance with its functionality. The JEDEC file used to program the GAL/PAL may contain in addition to the fuses list also a list of vectors to check the programmed chip. The format of the JEDEC file is well described, and the sections of verification vectors are described too.
In the XGPro V.11.81 program, there is a digital logic IC testing mode. You can create your own template for checking arbitrary devices. I tried to do this using the built-in toolkit. To check the GAL/PAL chip a large number of vectors required, and enter all of them through the proposed input interface seems not very productively. Is it possible to add to the XGPRO program the import of verification vectors from the JEDEC file? It would be very convenient, given that these vectors can be more than 100 pieces for one device. Agree, to create hundreds of vectors using an interface built into XGPRO.11.81, it will be necessary to click on "Pins Vector Set" drop-down lists from 1 hour of working time (the most optimistic forecast - a pair of seconds for one pin with the number of pins of 18). And this is without checking the entire table, and errors when transferring such a big bunch of data manually is highly possible.
Perhaps I missed some utility to convert a JEDEC or other text file with check vectors in the * .lgc format?
And more: in the description "T56_TL8666II User Guide.pdf" I could not found some information about time period during which the logical chip testing begins after power supply is on. To test the GAL containing the triggers after programming, this time is extremely important, since for some time after the power-on device is presetting these triggers in the initial state. In my case (GAL16V8D) it's 1us. It is not clear why, but when testing in TL866II +, some triggers are not reset before the start of the test. What happens before the start of the test - I don't know, maybe the pins of the chip are checked on the possible short to gnd, etc., and at this moment the initial state of the triggers can change. The point here is definitely not in my chip, as when checking manually (I have a device with old good togglers and LEDs) I can swear that all the triggers are reset when the power is suppressed as it should.

回复 1# uncleura

JEDEC does not seem to generate a logic test vector table

TOP

The JEDEC standard definitely has support for vectors to test the generated device. See, for example, page 1 (Introduction) at www.pldtool.com/pdf/jesd3c_jedecfmt.pdf. Programs that create JEDEC files, for example, for GAL/PAL, in addition to fuses, put check vectors in this file. File has simple and good documented format. Here is a part of JEDEC file generated with program WINCUPL:

*L01824 11111011111111111111111111111111
*L02048 01011111001100000011000000100000
*L02112 00000000010010111111111111111111
*L02144 11111111111111111111111111111111
*L02176 111111111111111101
*C8717
*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
*V0001 000101001N0HLHHHHHHN
*V0002 000001XXXN1HLZXZZXZN
*V0003 010111XXXN0HLHXHHXHN
*V0004 001111XXXN0LLHXHHXHN
*V0005 011111XXXN0LLHXHHXHN
*V0006 000111XXXN0HHHXHHXHN
*V0007 010111XXXN0HLHXHHXHN

Lines next to *P 1 2 3 .... are nothing but vectors to check target device after programming fuses.
V0001 means vector number 1
0 means logic 0 on input
1   means logic 1 on input
X means "not tested"
N means "power pin" (not tested)
H test that output is high
etc.

full list you can find on page 14 of document mentioned above.

TOP

返回列表 回复 发帖