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Device Logic IC Testing issue using ATF22V10C-15PC Pin 23 as Input/Output.
Device Logic IC Testing issue using ATF22V10C-15PC Pin 23 as Input/Output.
Do you have any idea what is causing this and how to correct this output state ERRORs?
"S-100 Dual IDE V3a board" uses two GAL22V10-15 Jameco sold me two PALCE22V10D-15PC as a substitute but the TL866II plus can't program that part as a GAL22V10. I got two ATF22V10C-15PC so I converted the PASASM PDS to WinCUPL .PLD to output a .JED file. Was able to Program the two GAL's with the Xgpro v12.50 TL866II plus firmware v04.02.131. To verify that they were programmed correctly I created two Xgpro Device Logic IC Tests for the two GAL's 。 Having problems with one of the equations in the 2nd GAL the truth table setup ERRORs with both output states.
Attached zip file contains the IDE_GAL2.PDS, .PLD, .LGC, and .JED files.
Tests:
#1 Testing results ERRORs with both output states.
#2 Same as #1 but swapped CS_8255 with bsVAL Result OK.
#3 Same as #1 but removed the OR of CS_8255 Result OK.
#4 Just CS_8255 Used both PALASM .jed & WinCupl .jed with the same Weird Result!
#5 Same as #3 but replaced !BRD_SEL with PORT_AB Result OK.
#1 Testing results ERRORs with both output states.
Input:
PIN 4 = !ADDR_DR;
PIN 5 = sOUT;
PIN 7 = !pWR;
Output:
PIN 18 = !BRD_SEL;
I/O:
PIN 23 = !CS_8255;
Equation:
BRD_SEL = CS_8255 # ADDR_DR & sOUT & pWR;
Truth Table:
Convert To: !CS_8255 !ADDR_DR sOUT !pWR | !BRD_SEL
--------------------- -------- -------------- ---|--- ------
Start value: 0 0 0 0 | H
0 0 0 1 | H
0 0 1 0 | L
0 0 1 1 | L or H error
0 1 0 0 | H
0 1 0 1 | H
0 1 1 0 | L or H error
0 1 1 1 | L or H error
1 0 0 0 | H
1 0 0 1 | H
1 0 1 0 | L
1 0 1 1 | L or H error
1 1 0 0 | H
1 1 0 1 | H
1 1 1 0 | L or H error
1 1 1 1 | L or H error
*--No effect
===================================================== ==========================
===================================================== ==========================
#2 Same as #1 but swapped CS_8255 with bsVAL Result OK.
Input:
PIN 2 = !bsVAL;
PIN 4 = !ADDR_DR;
PIN 5 = sOUT;
PIN 7 = !pWR;
Output:
PIN 18 = !BRD_SEL;
I/O:
Equation:
BRD_SEL = bsVAL # ADDR_DR & sOUT & pWR;
Truth Table:
Convert To: !bsVAL !ADDR_DR sOUT !pWR | !BRD_SEL
---------------------------------------- -------|---------
Start value: 0 0 0 0 | L
0 0 0 1 | L
0 0 1 0 | L
0 0 1 1 | L
0 1 0 0 | L
0 1 0 1 | L
0 1 1 0 | L
0 1 1 1 | L
1 0 0 0 | H
1 0 0 1 | H
1 0 1 0 | L
1 0 1 1 | H
1 1 0 0 | H
1 1 0 1 | H
1 1 1 0 | H
1 1 1 1 | H
===============================================================================
===============================================================================
#3 Same as #1 but removed the OR of CS_8255 Result OK. Input :
PIN 4 = !ADDR_DR;
PIN 5 = sOUT;
PIN 7 = !pWR;
Output:
PIN 18 = !BRD_SEL;
Equation:
BRD_SEL = ADDR_DR & sOUT & pWR;
Truth Table:
Convert To: !ADDR_DR sOUT !pWR | !BRD_SEL
----------------------------------- ----|---------
Start value: 0 0 0 | H
0 0 1 | H
0 1 0 | L
0 1 1 | H
1 0 0 | H
1 0 1 | H
1 1 0 | H
1 1 1 | H
==================================================================
====================================================================
#4 Just CS_8255 Used both PALASM .jed and WinCupl .jed same Weird Result!
Output:
PIN 18 = !BRD_SEL;
I/O:
PIN 23 = !CS_8255;
Equation:
BRD_SEL = CS_8255;
Truth Table:
Convert To: !CS_8255 | !BRD_SEL
----------------|---------
Start value: 0 | H
1 | H
*<--<< How can this happen ????
==========================================================================
===========================================================================
#5 Same as #3 but replaced !BRD_SEL with PORT_AB Result OK.
Input:
PIN 4 = !ADDR_DR;
PIN 5 = sOUT;
PIN 7 = !pWR;
Output:
PIN 14 = PORT_AB;
Equation:
PORT_AB = ADDR_DR & sOUT & pWR;
Truth Table:
Convert To: !ADDR_DR sOUT !pWR | PORT_AB
------------------------------------|---------
Start value: 0 0 0 | L
0 0 1 | L
0 1 0 | H
0 1 1 | L
1 0 0 | L
1 0 1 | L
1 1 0 | L
1 1 1 | L
============================================================================
============================================================================ |
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