XGecu Programmer Forums » Logic Test--Thank users for enthusiastic sharing » New type of clock signal

yovish 发表于 2021-4-6 02:37

New type of clock signal

Is it possible to introduce a second type of clock signal as shown in the picture?

Now there is only a signal type 010 ("C"), but adding a signal 101 ("K") would increase the possibilities of testing digital circuits.

admin 发表于 2021-4-6 15:44

1. set CLK PIN to 1
2 set [size=12px]CLK [/size][size=12px]PIN to 0 [/size]

3 set [size=12px]CLK [/size][size=12px]PIN to 1    [/size]

yovish 发表于 2021-4-6 17:03

I would suggest considering 2 new signals: "U" - Up (01) and "D" - Down (10) ...

yovish 发表于 2021-4-6 17:25

[b]回复 [url=http://forums.xgecu.com/redirect.php?goto=findpost&pid=628&ptid=208]2#[/url] [i]admin[/i] [/b]


   It is about signals that change during other signals...
This is easier to understand when you work with digital signals...

yovish 发表于 2021-6-19 07:34

Competitive companies know that it is worth being more flexible and you need to improve your products...

Here is a description of the signals for logic tests.

; Characters for testing vector are as follows:
;                               G...apply GND
;                               V...apply VCC
;                               X...Don't care
;                               0...input low level
;                               1...input high level
;                               C...input L-H-L puls
;                               [b]K...input H-L-H puls[/b]
;                               L...expected output is low level
;                               H...expected output is high level
;                               Z...expected output is float

admin 发表于 2021-6-20 09:09

[b]回复 [url=http://forums.xgecu.com/redirect.php?goto=findpost&pid=859&ptid=208]5#[/url] [i]yovish[/i] [/b]

Later, when we have time, we will add this function .
Temporary method： 3-items vector table 1 - 0 - 1

yovish 发表于 2021-6-21 03:41

[b]回复 [url=http://forums.xgecu.com/redirect.php?goto=findpost&pid=861&ptid=208]6#[/url] [i]admin[/i] [/b]

Just don't underestimate it and don't forget it. Please consider also other quite simple improvements in logic tests (eg clock signal "U" - up "01" and "D" - down "10" and other easy modifications to improve the editing of logical tests).
Your programmers, at least in logic tests, can become much better than the much more expensive competition, costing $ 500-1000.
I still have at least 30-40 new tests to do, which will further enrich the list of logic integrated circuits tested.

admin 发表于 2021-6-21 08:47

[b]回复 [url=http://forums.xgecu.com/redirect.php?goto=findpost&pid=865&ptid=208]7#[/url] [i]yovish[/i] [/b]

   You are right, we will improve it in the future

yovish 发表于 2021-8-11 05:57

Thank you very much!

查看完整版本: New type of clock signal